Embedded Systems Drivers: Stellaris Tiva C Series cortex M4123G LaunchPad Voltameter And Frequency Generator from 1 HZ ~ 5 MHZ

This is a cooperation work between me and Eng Osama Ghanem and Eng Mennat Allah Hosny

#############################
### This code based on Keil IDE ###
#############################

System is include LCD and keypad drivers for inputs and outputs
please check our previous post :

http://embedded-systems-drivers-launchpad.blogspot.com/2014/03/tiva-c-series-m4123g-launchpad-cortex.html

===========

when system run you should see on the this options on the LCD
-1 voltmeter
-2 Freq Synthesizer
then you should use the 2 on_chip switches SW1 and SW2 for input
===================================================

1-Voltameter :

V input to kit is connected to PORTE PIN PE4

========== ADC.h file =========
#include "tm4c123gh6pm.h"

void ADC0_InitSWTriggerSeq3_Ch9(void);
unsigned long ADC0_InSeq3(void);

============================

===========ADC.c file==========

#include"ADC.h"

void ADC0_InitSWTriggerSeq3_Ch9(void){ volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port E
delay = SYSCTL_RCGC2_R; // allow time for clock to stabilize
GPIO_PORTE_DIR_R &= ~0x04; // 2) make PE4 input
GPIO_PORTE_AFSEL_R |= 0x04; // 3) enable alternate function on PE2
GPIO_PORTE_DEN_R &= ~0x04; // 4) disable digital I/O on PE2
GPIO_PORTE_AMSEL_R |= 0x04; // 5) enable analog function on PE2
SYSCTL_RCGC0_R |= 0x00010000; // 6) activate ADC0
delay = SYSCTL_RCGC2_R;
SYSCTL_RCGC0_R &= ~0x00000300; // 7) configure for 125K
ADC0_SSPRI_R = 0x0123; // 8) Sequencer 3 is highest priority
ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3
ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger
ADC0_SSMUX3_R &= ~0x000F; // 11) clear SS3 field
ADC0_SSMUX3_R += 9; // set channel Ain9 (PE4)
ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0
ADC0_ACTSS_R |= 0x0008; // 13) enable sample sequencer 3
}
unsigned long ADC0_InSeq3(void){ unsigned long result;
ADC0_PSSI_R = 0x0008; // 1) initiate SS3
while((ADC0_RIS_R&0x08)==0){}; // 2) wait for conversion done
result = ADC0_SSFIFO3_R&0xFFF; // 3) read result
ADC0_ISC_R = 0x0008; // 4) acknowledge completion
return result;
}

==================================================

2-Frequency Generator using PLL and SysTick:

Enter the required frequency using the keypad and then press enter button on keypad

and the output will be on the PORTA PIN PA6

====PLL.h file===

// PLL.h

// Runs on LM4F120/TM4C123

// A software function to change the bus frequency using the PLL.

// Daniel Valvano

// September 10, 2013

/* This example accompanies the book

"Embedded Systems: Real Time Interfacing to Arm Cortex M Microcontrollers",

Program 2.10, Figure 2.37

You may use, edit, run or distribute this file

as long as the above copyright notice remains

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED

OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,

OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

For more information about my classes, my research, and my books, see

http://users.ece.utexas.edu/~valvano/

// The #define statement SYSDIV2 initializes

// the PLL to the desired frequency.

#define SYSDIV2 4

// bus frequency is 400MHz/(SYSDIV2+1) = 400MHz/(4+1) = 80 MHz

// configure the system to get its clock from the PLL

void PLL_Init(void);

SYSDIV2 Divisor Clock (MHz)

0 1 reserved

1 2 reserved

2 3 reserved

3 4 reserved

4 5 80.000

5 6 66.667

6 7 reserved

7 8 50.000

8 9 44.444

9 10 40.000

10 11 36.364

11 12 33.333

12 13 30.769

13 14 28.571

14 15 26.667

15 16 25.000

16 17 23.529

17 18 22.222

18 19 21.053

19 20 20.000

20 21 19.048

21 22 18.182

22 23 17.391

23 24 16.667

24 25 16.000

25 26 15.385

26 27 14.815

27 28 14.286

28 29 13.793

29 30 13.333

30 31 12.903

31 32 12.500

32 33 12.121

33 34 11.765

34 35 11.429

35 36 11.111

36 37 10.811

37 38 10.526

38 39 10.256

39 40 10.000

40 41 9.756

41 42 9.524

42 43 9.302

43 44 9.091

44 45 8.889

45 46 8.696

46 47 8.511

47 48 8.333

48 49 8.163

49 50 8.000

50 51 7.843

51 52 7.692

52 53 7.547

53 54 7.407

54 55 7.273

55 56 7.143

56 57 7.018

57 58 6.897

58 59 6.780

59 60 6.667

60 61 6.557

61 62 6.452

62 63 6.349

63 64 6.250

64 65 6.154

65 66 6.061

66 67 5.970

67 68 5.882

68 69 5.797

69 70 5.714

70 71 5.634

71 72 5.556

72 73 5.479

73 74 5.405

74 75 5.333

75 76 5.263

76 77 5.195

77 78 5.128

78 79 5.063

79 80 5.000

80 81 4.938

81 82 4.878

82 83 4.819

83 84 4.762

84 85 4.706

85 86 4.651

86 87 4.598

87 88 4.545

88 89 4.494

89 90 4.444

90 91 4.396

91 92 4.348

92 93 4.301

93 94 4.255

94 95 4.211

95 96 4.167

96 97 4.124

97 98 4.082

98 99 4.040

99 100 4.000

100 101 3.960

101 102 3.922

102 103 3.883

103 104 3.846

104 105 3.810

105 106 3.774

106 107 3.738

107 108 3.704

108 109 3.670

109 110 3.636

110 111 3.604

111 112 3.571

112 113 3.540

113 114 3.509

114 115 3.478

115 116 3.448

116 117 3.419

117 118 3.390

118 119 3.361

119 120 3.333

120 121 3.306

121 122 3.279

122 123 3.252

123 124 3.226

124 125 3.200

125 126 3.175

126 127 3.150

127 128 3.125

=============================================

============PLL.c file===========

// PLL.c

// Runs on LM4F120/TM4C123

// A software function to change the bus frequency using the PLL.

// Daniel Valvano

// September 10, 2013

/* This example accompanies the book

"Embedded Systems: Real Time Interfacing to Arm Cortex M Microcontrollers",

Program 2.10, Figure 2.37

You may use, edit, run or distribute this file

as long as the above copyright notice remains

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED

OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,

OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

For more information about my classes, my research, and my books, see

http://users.ece.utexas.edu/~valvano/

#include "PLL.h"

// The #define statement SYSDIV2 in PLL.h

// initializes the PLL to the desired frequency.

// bus frequency is 400MHz/(SYSDIV2+1) = 400MHz/(7+1) = 50 MHz

// see the table at the end of this file

#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))

#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status

#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))

#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value

#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz Crystal

#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz Crystal

#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz Crystal

#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))

#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2

#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200

// MHz

#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2

#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2

#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2

#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2

#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2

#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC

// configure the system to get its clock from the PLL

void PLL_Init(void){

// 0) configure the system to use RCC2 for advanced features

// such as 400 MHz PLL and non-integer System Clock Divisor

SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2;

// 1) bypass PLL while initializing

SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2;

// 2) select the crystal value and oscillator source

SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M; // clear XTAL field

SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ;// configure for 16 MHz crystal

SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M;// clear oscillator source field

SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO;// configure for main oscillator source

// 3) activate PLL by clearing PWRDN

SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2;

// 4) set the desired system divider and the system divider least significant bit

SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400; // use 400 MHz PLL

SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000) // clear system clock divider field

+ (SYSDIV2<<22); // configure for 80 MHz clock

// 5) wait for the PLL to lock by polling PLLLRIS

while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){};

// 6) enable use of PLL by clearing BYPASS

SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2;

}

SYSDIV2 Divisor Clock (MHz)

0 1 reserved

1 2 reserved

2 3 reserved

3 4 reserved

4 5 80.000

5 6 66.667

6 7 reserved

7 8 50.000

8 9 44.444

9 10 40.000

10 11 36.364

11 12 33.333

12 13 30.769

13 14 28.571

14 15 26.667

15 16 25.000

16 17 23.529

17 18 22.222

18 19 21.053

19 20 20.000

20 21 19.048

21 22 18.182

22 23 17.391

23 24 16.667

24 25 16.000

25 26 15.385

26 27 14.815

27 28 14.286

28 29 13.793

29 30 13.333

30 31 12.903

31 32 12.500

32 33 12.121

33 34 11.765

34 35 11.429

35 36 11.111

36 37 10.811

37 38 10.526

38 39 10.256

39 40 10.000

40 41 9.756

41 42 9.524

42 43 9.302

43 44 9.091

44 45 8.889

45 46 8.696

46 47 8.511

47 48 8.333

48 49 8.163

49 50 8.000

50 51 7.843

51 52 7.692

52 53 7.547

53 54 7.407

54 55 7.273

55 56 7.143

56 57 7.018

57 58 6.897

58 59 6.780

59 60 6.667

60 61 6.557

61 62 6.452

62 63 6.349

63 64 6.250

64 65 6.154

65 66 6.061

66 67 5.970

67 68 5.882

68 69 5.797

69 70 5.714

70 71 5.634

71 72 5.556

72 73 5.479

73 74 5.405

74 75 5.333

75 76 5.263

76 77 5.195

77 78 5.128

78 79 5.063

79 80 5.000

80 81 4.938

81 82 4.878

82 83 4.819

83 84 4.762

84 85 4.706

85 86 4.651

86 87 4.598

87 88 4.545

88 89 4.494

89 90 4.444

90 91 4.396

91 92 4.348

92 93 4.301

93 94 4.255

94 95 4.211

95 96 4.167

96 97 4.124

97 98 4.082

98 99 4.040

99 100 4.000

100 101 3.960

101 102 3.922

102 103 3.883

103 104 3.846

104 105 3.810

105 106 3.774

106 107 3.738

107 108 3.704

108 109 3.670

109 110 3.636

110 111 3.604

111 112 3.571

112 113 3.540

113 114 3.509

114 115 3.478

115 116 3.448

116 117 3.419

117 118 3.390

118 119 3.361

119 120 3.333

120 121 3.306

121 122 3.279

122 123 3.252

123 124 3.226

124 125 3.200

125 126 3.175

126 127 3.150

127 128 3.125

======================================

==========Main Function main.c file ==========

#include "tm4c123gh6pm.h"

#include"LCD.h"

#include"ADC.h"

#include"KEYPAD.h"

#include"PLL.h"

#include<math.h>

/*#ifdef __TI_COMPILER_VERSION__

//Code Composer Studio Code

void Delay(unsigned long ulCount){

__asm ( " subs r0, #1\n"

" bne Delay\n"

" bx lr\n");

}

#else */

//Keil uVision Code

__asm void

Delay(unsigned long ulCount)

{

subs r0, #1

bne Delay

bx lr

}

void PortE_Init(void){ volatile unsigned long delay;

SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port E

delay = SYSCTL_RCGC2_R; // allow time for clock to start

// only PF0 needs to be unlocked, other bits can't be locked

GPIO_PORTE_AMSEL_R = 0x00; // 3) disable analog on PF

GPIO_PORTE_PCTL_R = 0x00000000; // 4) PCTL GPIO on PF4-0

GPIO_PORTE_DIR_R = 0xFF; // 5) PF4,PF0 in, PF3-1 out

GPIO_PORTE_AFSEL_R = 0x00; // 6) disable alt funct on PF7-0

//GPIO_PORTE_PUR_R = 0x11; // enable pull-up on PF0 and PF4

GPIO_PORTE_DEN_R = 0xFF; // 7) enable digital I/O on PF4-0

}*/

void PortA_Init(void){ volatile unsigned long delay;

SYSCTL_RCGC2_R |= 0x00000001; // 1) activate clock for Port A

delay = SYSCTL_RCGC2_R; // allow time for clock to start

// only PF0 needs to be unlocked, other bits can't be locked

GPIO_PORTA_AMSEL_R = 0x00; // 3) disable analog on PA

GPIO_PORTA_PCTL_R = 0x00000000; // 4) PCTL GPIO on PA

GPIO_PORTA_DIR_R = 0xFF; // 5) PA out

GPIO_PORTA_AFSEL_R = 0x00; // 6) disable alt funct on PA

GPIO_PORTA_PUR_R = 0x00; // enable pull-up on PA5,6,7

GPIO_PORTA_DEN_R = 0xFF; // 7) enable digital I/O on PA

}

void PortF_Init(void){ volatile unsigned long delay;

SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOF; // 1) activate clock for Port F

delay = SYSCTL_RCGC2_R; // allow time for clock to start

GPIO_PORTF_LOCK_R = 0x4C4F434B; // 2) unlock GPIO Port F

GPIO_PORTF_CR_R = 0x1F; // allow changes to PF4-0

// only PF0 needs to be unlocked, other bits can't be locked

GPIO_PORTF_AMSEL_R = 0x00; // 3) disable analog on PF

GPIO_PORTF_PCTL_R = (GPIO_PORTF_PCTL_R&0xFFF0FFFF)+0x00000000; // 4) PCTL GPIO on PF4-0

GPIO_PORTF_DIR_R = 0x0E; // 5) PF4,PF0 in, PF3-1 out

GPIO_PORTF_AFSEL_R = 0x00; // 6) disable alt funct on PF7-0

GPIO_PORTF_PUR_R = 0x11; // enable pull-up on PF0 and PF4

GPIO_PORTF_DEN_R = 0x1F; // 7) enable digital I/O on PF4-0

}

void _delay_ms(unsigned long time)

{

time = ((time/375)*1000000);

while(time)

{

time--;

}

void Voltmeter_Func(){

unsigned long ADC;

ADC0_InitSWTriggerSeq3_Ch9();

LCD_Clear();

LCD_Goto(1,1);

LCD_Send_String("Volt is: ");

LCD_Goto(2,13);

LCD_Send_String("V");

while(1){

ADC=ADC0_InSeq3();

LCD_Goto(2,3);

LCD_Send_Float((float)ADC*0.00080566);

_delay_ms(2000);

}

void Freq_Synth_Func(){

unsigned char count = 0;

char input[16] = {0};

char read = 0;

unsigned long num = 0;

float convert;

unsigned char i = 0;

PLL_Init();

Keypad_Init();

LCD_Clear();

LCD_Goto(1,1);

LCD_Send_String("Freq Synth O/P:");

LCD_Goto(2,10);

LCD_Send_String("Hz");

LCD_Goto(2,1);

while((read =Keypad_Read())!= 16) //read opearnds and operator from user

{

input[count] = key_pressed(read); //save inputs

LCD_Send_Character(input[count]+48); //display inputs on LCD display

count++;

}

for(i=0;i<count;i++)

{

num += (input[i])*(pow(10,(count-i-1)));

}

convert=((int)((1.0/num)/(0.000000125*0.5)));

while(1){

GPIO_PORTA_DATA_R = 0x40; // turn on LED1 (blue)

Delay(convert); // delay ~0.5 sec at 80 MHz

GPIO_PORTA_DATA_R = 0x00; // turn off LED1 (blue)

Delay(convert);

}

int main()

{volatile unsigned long delay;

PortF_Init();

LCD_init();

LCD_Goto(1,1);

LCD_Send_String("1: Voltmeter");

LCD_Goto(2,1);

LCD_Send_String("2: Freq Synth");

while(1){

if((GPIO_PORTF_DATA_R&0x10)==0x00){

Voltmeter_Func();

}else if ((GPIO_PORTF_DATA_R&0x01)==0x00){

LCD_Clear();

Freq_Synth_Func();

}

========== End of the Project .. Thanks====
Your comments will be appreciated :)

Embedded Systems Drivers

Saturday 29 March 2014

Stellaris Tiva C Series cortex M4123G LaunchPad Voltameter And Frequency Generator from 1 HZ ~ 5 MHZ

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